Co-pending patent application Ser. No. 07/589,222 by Saxe et al. for an "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference, describes a fast-in, slow-out (FISO) analog data acquisition system in which a tapped delay line, or some other source of closely spaced-in-time sequential timing signals, clocks high speed analog data into analog capture cells, which then transfer that data to a more extensive analog memory array. When data acquisition is complete, the voltage levels stored in the analog memory array are transferred out and quantified.
A variety of tapped delay lines and other sources of closely spaced-in-time sequential timing signals are described in the U.S. patent Ser. No. 07/589,222 application. Another co-pending patent application, Ser. No. 07/824,434 by the present inventor for a "High Speed Sample and Hold Signal Generator", hereby incorporated by reference, describes several other ways to generate closely spaced-in-time sequential timing signals.
The analog capture cells and the analog memory array described in the U.S. patent Ser. No. 07/589,222 application are both based on capacitors and CMOS (Complementary Metal Oxide Semiconductor) transistors. As the size of such an analog memory array is increased, it presents increasing input capacitance to the analog capture cells that must transfer voltage levels to it. This increasing capacitance degrades the quality of the data acquired and ultimately limits the acquisition speed of the system.
Charge coupled devices present a very low input capacitance and have previously been used as sampling devices and storage units for analog acquisition systems. U.S. Pat. No. 4,648,072 to Hayes et al. for "High Speed Data Acquisition Utilizing Multiplex Charge Transfer Devices", hereby incorporated by reference, discloses a data acquisition system that utilizes CCDs. Referring to FIG. 2 of the '072 patent, in this system the signal to be sampled is applied to two diodes (68,70) which are each input to a data channel. Each data channel contains a serial input register (62,62') of CCDs. The serial input registers of CCDs are 16 stages long and each provide input to a 16.times.33 stage storage array of CCDs, which in turn provide input to 16-stage CCD output registers. This serial-parallel-serial (SPS) organization provides for fast-in, slow-out (FISO) operation.
In the system described in the '072 patent, samples are moved along each part of the SPS structures of both channels by a 4-phase clock signal. The data acquisition rate is determined by the frequency of a two phase sampling clock (S1/S3) that clocks the signals in each channel from the input diodes to the input of the serial CCD input registers. Two samples of the signal being acquired are clocked into the first serial CCD input register by each cycle of the sampling clock, so that two consecutive samples of the input signal are acquired during each transfer clock cycle, one by each channel. To keep up with the incoming data, the clocks (.phi.1A-.phi.4A) that move the data through the first, serial portion of the SPS structure must operate at the same speed as the sampling clocks (S1/S3). Since clocks for moving data through CCDs must have a large voltage swing and producing that large voltage swing at high frequencies requires very high amplifier slew rates, the overall acquisition speed of this system is limited by the CCD clock rate.
U.S. Pat. No. 4,951,302 to Peter et al. for "Charge-Coupled Device Shift Register", hereby incorporated by reference, discloses a two-phase CCD shift register having a four-phase input section to boost data acquisition speeds. It also employs the SPS-type architecture described in connection with the '072 patent.